ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 243

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.7.4
21.7.5
21.8
21.8.1
8077H–AVR–12/09
Asynchronous Data Reception
Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Clock Recovery
A disabling of the Receiver will be immediate. The Receiver buffer will be flushed, and data from
ongoing receptions will be lost.
If the receive buffer has to be flushed during normal operation, read the DATA location until the
Receive Complete Interrupt Flags is cleared.
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the incoming asynchronous serial
frames at the RxD pin to the internally generated baud rate clock. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
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rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-
cess. Note the larger time variation when using the Double Speed mode of operation. Samples
denoted zero are samples done when the RxD line is idle, i.e. no communication activity.
Figure 21-6. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Sample 1 denotes the first zero-sample as shown in the
figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples
4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure)
to decide if a valid start bit is received. If two or more of these three samples have a low level
(the majority wins), the start bit is accepted. The clock recovery logic is synchronized and the
data recovery can begin. If two or more of the three samples have a high level the start bit is
rejected as a noise spike and the Receiver starts looking for the next high to low-transition. The
synchronization process is repeated for each start bit.
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
0
0
IDLE
illustrates the sampling process of the start bit of an incoming frame. The sample
0
1
1
2
3
2
4
5
3
6
7
4
8
START
9
5
10
11
6
12
13
7
14
15
8
XMEGA A
16
1
1
Figure 21-6
2
BIT 0
3
2
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