ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 140

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.14.7
13.14.8
13.14.9
8077H–AVR–12/09
OUTCLR - Data Output Value Clear Register
OUTTGL - Data Output Value Toggle Register
IN - Data Input Value Register
• Bit 7:0 - OUTSET[7:0]: Data Output Value Set
This register can be used instead of a Read-Modify-Write to set the output value on individual
pins to one. Writing a one to a bit will set the corresponding bit in the OUT register. Reading this
register will return the value in the OUT register.
• Bit 7:0 - OUTCLR[7:0]: Data Output Value Clear
This register can be used instead of a Read-Modify-Write to set the output value on individual
pins to zero. Writing a one to a bit will clear the corresponding bit in the OUT register. Reading
this register will return the value in the OUT register.
• Bit 7:0 - OUTTGL[7:0]: Port Data Output Value Toggle
This register can be used instead of a Read-Modify-Write to toggle the output value on individual
pins. Writing a one to a bit will toggle the corresponding bit in the OUT register. Reading this reg-
ister will return the value in the OUT register.
• Bit 7:0 - IN[7:0]: Data Input Value
This register shows the value present on the pins if the digital input driver is enabled. INn shows
the value of pin n on the port.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
5
0
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OUTCLR[7:0]
OUTTGL[7:0]
IN[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
OUTCLR
OUTTGL
IN
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