ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 139

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.14.3
13.14.4
13.14.5
13.14.6
8077H–AVR–12/09
DIRCLR - Data Direction Clear Register
DIRTGL - Data Direction Toggle Register
OUT - Data Output Value
OUTSET - Data Output Value Set Register
• Bit 7:0 - DIRCLR[7:0]: Port Data Direction Clear
This register can be used instead of a Read-Modify-Write to set individual pins as input. Writing
a one to a bit will clear the corresponding bit in the DIR register. Reading this register will return
the value of the DIR register.
• Bit 7:0 - DIRTGL[7:0]: Port Data Direction Toggle
This register can be used instead of a Read-Modify-Write to toggle the direction on individual
pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this reg-
ister will return the value of the DIR register.
• Bit 7:0 - OUT[7:0]: Port Data Output value
This register sets the data output value for the individual pins in the port. If OUTn is written to
one, pin n is driven high. If OUTn is written to zero, pin n is driven low. For this setting to have
any effect the pin direction must be set as output.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
OUTSET[7:0]
DIRCLR[7:0]
DIRTGL[7:0]
OUT[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OUTSET
DIRCLR
DIRTGL
OUT
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