ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 153

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4
14.5
8077H–AVR–12/09
Clock and Event Sources
Double Buffering
The Timer/Counter can be clocked from the Peripheral Clock (clk
tem, and
Figure 14-3. Clock and Event Selection
The Peripheral Clock is fed into the Common Prescaler (common for all Timer/Counters in a
device). A selection of the prescaler outputs is directly available for the Timer/Counter. In addi-
tion the whole range from 1 to 2
Each Timer/Counter has separate clock selection (CLKSEL), to select one of the prescaler out-
puts directly or an event channel as the Counter (CNT) input. This is referred to as Normal
Operation for the Counter, for details refer to
Event System, any event source such as an external clock signal on any I/O pin can be used as
clock input.
In addition the Timer/Counter can be controlled via the Event System. The Event Selection
(EVSEL) and Event Action (EVACT) settings can be used to trigger an event action from one or
more events. This is referred to as Event Action Controlled Operation for the Counter, for details
refer to
tion is used, the clock selection must be set to us an event channel as the Counter input.
By default no clock input is selected and the Timer/Counter is not running (OFF state).
The Period Register and the CC registers are all double buffered. Each buffer registers have an
associated Buffer Valid (BV) flag, which indicate that the buffer contains a valid, i.e. a new value
that is to be copied into the belonging period or compare register. For the Period register and for
the CC channels when used for compare operation, the Buffer Valid flag is set when data is writ-
ten to the buffer register and cleared on UPDATE condition. This is shown for a compare
register in
clk
”Event Action Controlled Operation” on page
PER
Figure 14-3
Figure 14-4 on page
CLKSEL
EVACT
EVSEL
Prescaler
Common
shows the clock and event selection logic.
{1,2,4,8,64,256,1024}
154.
15
(Encoding)
times prescaling is available through the Event System.
clk /
clk
2
{0,...,15}
PER
/
”Normal Operation” on page
Event System
event channels
155. When Event Action Controlled Opera-
PER
) and from the Event Sys-
Control Logic
events
XMEGA A
155. By using the
CNT
153