ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 236

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8077H–AVR–12/09
Figure 21-1. USART Block Diagram
The Clock Generation logic has a fractional baud rate generator that is able to generate a wide
range of USART baud rates. It also includes synchronization logic for external clock input in syn-
chronous slave operation.
The Transmitter consists of a single write buffer (DATA), a shift register, Parity Generator and
control logic for handling different frame formats. The write buffer allows continuous data trans-
mission without any delay between frames.
The Receiver consists of a two level FIFO receive buffer (DATA), and a shift register. Data and
clock recovery units ensure robust synchronization and noise filtering during asynchronous data
reception. It includes frame error, buffer overflow and parity error detection.
When the USART is set in Master SPI compliant mode, all USART specific logic is disabled,
leaving the transmit and receive buffers, shift registers, and Baud Rate Generator enabled. Pin
control and interrupt generation is identical in both modes. The registers are used in both
modes, but the functionality differs for some control settings.
An IRCOM Module can be enabled for one USART to support IrDA 1.4 physical compliant pulse
modulation and demodulation for baud rates up to 115.2 kbps. For details refer to
”IRCOM - IR Communication Module” on page 256
CTRLA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
FRACTIONAL DEVIDE
DATA (Transmit)
DATA (Receive)
BSEL [H:L]
for details.
CTRLB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
OSC
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
CTRLC
XMEGA A
XCK
RxD
TxD
Section 22.
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