ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 244

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.8.2
21.8.3
8077H–AVR–12/09
Asynchronous Data Recovery
Asynchronous Operational Range
The data recovery unit uses sixteen samples in Normal mode and eight samples in Double
Speed mode for each bit.
ity bits.
Figure 21-7. Sampling of Data and Parity Bit
As for start bit detection, identical majority voting technique is used on the three center samples
(indicated with sample numbers inside boxes) for deciding of the logic level of the received bit.
This majority voting process acts as a low pass filter for the received signal on the RxD pin. The
process is repeated for each bit until a complete frame is received. Including the first, but exclud-
ing additional stop bits. If the stop bit sampled has a logic 0 value, the Frame Error (FERR) Flag
will be set.
Figure 21-8 on page 244
beginning of the next frame's start bit.
Figure 21-8. Stop Bit Sampling and Next Start Bit Sampling
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Stop Bit Sampling and Next Start Bit Sampling. For Double Speed mode the
first low level must be delayed to (B). (C) marks a stop bit of full length at nominal baud rate. The
early start bit detection influences the operational range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If an external Transmitter is sending on bit rates that
are too fast or too slow, or the internally generated baud rate of the Receiver does not match the
external source’s base frequency, the Receiver will not be able to synchronize the frames to the
start bit.
(CLK2X = 0)
(CLK2X = 1)
(CLK2X = 0)
(CLK2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
1
1
1
1
Figure 21-7 on page 244
2
2
shows the sampling of the stop bit in relation to the earliest possible
3
2
3
2
4
4
5
3
5
3
6
6
7
4
7
4
8
8
STOP 1
shows the sampling process of data and par-
BIT n
9
5
9
5
10
10
(A)
0/1
11
6
6
0/1
12
(B)
0/1
0/1
13
7
14
15
8
XMEGA A
16
(C)
1
1
244