ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 246

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9
8077H–AVR–12/09
The Impact of Fractional Baud Rate Generation
Table 21-4.
The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receiver's system clock
will always have some minor instability. In addition, the baud rate generator can not always do
an exact division of the peripheral clock frequency to get the baud rate wanted. In this case the
BSEL and BSCALE value should be selected to give the lowest possible error.
Fractional baud rate generation is possible for asynchronous operation due to the relatively high
number of clock cycles (i.e. samples) for each frame. Each bit is sampled sixteen times, but only
the center samples are of importance. This leaves some slack for each bit. Not only that, but the
total number of samples for one frame is also relatively high. Given a 1-start, 8-data, no-parity,
and 1-stop bit frame format, and assumes that normal speed mode is used, the total number of
samples for a frame is, (1+8+1)*16, or 160. As earlier stated, the UART can tolerate plus minus
some samples. The critical factor is the time from the falling edge of the start bit (i.e. the clock
synchronization) to the last bit's (i.e. the first stop bit) value is recovered.
Standard baud rate generators have the unwanted property of having large frequency steps
between high baud rate settings. Worst case is found between BSEL value 0x000 and 0x001.
Going from an BSEL value of 0x000 for which has a 10-bit frame of 160 samples, to an BSEL
value 0x001 with 320 samples, shows a 50% change in frequency. However, when increasing
the BSEL values the step change will quickly decrease. Ideally the step size should be small
even between the fastest baud rates. This is where the advantage of the fractional baud rate
generator emerges.
In principle the fractional baud rate generator works by doing uneven counting and distributing
the error evenly over the entire frame. A typical count sequence for an ordinary baud rate gener-
ator is:
2, 1, 0, 2, 1, 0, 2, 1, 0, 2, …
which has an even period time. A baud rate clock tick each time the counter reaches zero, and a
sample of the received signal on RXD is taken for each baud rate clock tick. For the fractional
baud rate generator the count sequence can have an uneven period:
2, 1, 0, 3, 2, 1, 0, 2, 1, 0, 3, 2, …
In this example an extra cycle is added every second cycle. This gives a baud rate clock tick jit-
ter, but the average period has been increased by a fraction, more precisely 0.5 clock cycles.
The impact of the fractional baud rate generation is that the step size between baud rate settings
has been reduced. Given a scale factor of -1 the worst-case step, then becomes from 160 to 240
#(Data + Parity Bit)
10
D
8
9
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(CLK2X = 1) (Continued)
R
slow
96.00
96.39
96.70
(%)
R
103.90
103.53
103.23
fast
(%)
Max Total Error (%)
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
Recommended Max
Receiver Error (%)
XMEGA A
± 1.5
± 1.5
± 1.0
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