ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 53

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13
5.13.1
8077H–AVR–12/09
Register Description – DMA Controller
CTRL - DMA Control Register
• Bit 7 - ENABLE: DMA Enable
Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit is writ-
ten to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty and the
DMA data transfer is aborted.
• Bit 6 - RESET: DMA Software Reset
Setting this bit enables the software reset. This bit is automatically cleared when reset is com-
pleted. This bit can only be set when the DMA Controller is disabled (ENABLE = 0).
• Bit 5:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - DBUFMODE[1:0]: DMA Double Buffer Mode
These bits enables the double buffer on the different channels according to
Table 5-1.
• Bit 1:0 - PRIMODE[1:0]: DMA Channel Priority Mode
These bits determine the internal channel priority according to
Table 5-2.
Bit
+0x00
Read/Write
Initial Value
DBUFMODE[1:0]
PRIMODE[1:0]
00
01
10
11
00
01
10
11
ENABLE
R/W
DMA Double Buffer settings
DMA Channel Priority settings
7
0
Group Configuration
Group Configuration
RESET
R/W
6
0
CH0RR123
CH01RR23
CH01CH23
DISABLED
RR0123
CH0123
CH01
CH23
R
5
0
-
4
R
0
-
Description
Round Robin
Channel0 > Round Robin (Channel 1, 2 and 3)
Channel0 > Channel1 > Round Robin (Channel 2 and
3)
Channel0 > Channel1 > Channel2 > Channel3
Description
No double buffer enabled
Double buffer enabled on channel0/1
Double buffer enabled on channel2/3
Double buffer enabled on channel0/1 and channel2/3
R/W
DBUFMODE[1:0]
3
0
R/W
2
0
Table
5-2.
R/W
1
0
PRIMODE[1:0]
Table
XMEGA A
R/W
0
0
5-1.
CTRL
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