ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 1076

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

41.11.6
41.11.6.1
Table 41-47. SMC Read Signals - NRD Controlled (READ_MODE = 1)
1076
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
SAM3S Preliminary
SMC Timings
Parameter
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
NCS low before NRD High
NRD Pulse Width
Read Timings
A0 - A22 Valid before NRD High
VDDIO Supply
Figure 41-25. Min and Max Access Time of Output Signals
SMC Timings are given with the following conditions.
VDDIO = 1.62V @ 30 pF
VDDIO = 3V @ 50 pF
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables t
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
TK (CKI =0)
TK (CKI =1)
HOLD SETTINGS (nrd hold ≠ 0)
nrd pulse - ncs
t
(nrd setup +
CPMCK
(nrd setup +
t
TF/TD
CPMCK
t
nrd pulse)*
nrd pulse *
rd setup) *
CPMCK
CPMCK
1.8V
31.3
25
0
0
+ 13.5
- 6.7
is MCK period. Timing extraction
+ 14
(2)
Min
nrd pulse - ncs
t
(nrd setup +
(nrd setup +
CPMCK
t
t
nrd pulse)*
nrd pulse *
rd setup) *
CPMCK
CPMCK
3.3V
28.5
20.4
SSC
0
0
SSC
+ 14.5
- 3.6
(3)
+ 15
0max
0min
1.8V
(2)
Max
3.3V
6500C–ATARM–8-Feb-11
(3)
Units
ns
ns
ns
ns
ns
ns
ns