ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 153

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.20.2
• SETENA
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, assert-
ing its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its
priority.
6500C–ATARM–8-Feb-11
31
23
15
7
Interrupt Set-enable Registers
30
22
14
6
The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See:
The bit assignments are:
• the register summary in
•
Table 10-28 on page 152
29
21
13
5
28
20
12
4
Table 10-27 on page 151
SETENA bits
SETENA bits
SETENA bits
SETENA bits
for which interrupts are controlled by each register.
27
19
11
3
for the register attributes
26
18
10
2
SAM3S Preliminary
25
17
9
1
24
16
8
0
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