ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 400

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.15.4
Register Name:
Addresses:
Access Type:
• READ_MODE:
1: The read operation is controlled by the NRD signal.
0: The read operation is controlled by the NCS signal.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
0: The write operation is controlled by the NCS signal.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
400
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
Value
31
23
15
–
–
–
7
–
0
1
2
3
SAM3S Preliminary
SMC MODE Register
Name
DISABLED
FROZEN
READY
30
22
14
SMC_MODE[0..4]
0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3], 0x400E004C [4]
Read-write
–
–
–
6
–
29
21
13
–
5
Description
Disabled
Reserved
Frozen Mode
Ready Mode
EXNW_MODE
DBW
PS
TDF_MODE
28
20
12
4
27
19
11
–
–
3
–
26
18
10
–
–
2
–
TDF_CYCLES
WRITE_MODE
25
17
–
9
–
1
6500C–ATARM–8-Feb-11
READ_MODE
PMEN
24
16
8
–
0