ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 851

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36.6.2.2
6500C–ATARM–8-Feb-11
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
defined by CDTY in the
generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
reset at 0.
PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
(
------------------------------- -
(
------------------------------------------ -
(
------------------------------------------ -
(
----------------------------------------------------- -
X
CRPD
2
2
duty cycle
duty cycle
×
×
×
MCK
X
CPRD
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
“PWM Channel Period Register” on page 920
)
×
=
DIVA
=
)
)
(
----------------------------------------------------------------------------------------------------------- -
(
----------------------------------------------------------------------------------------------------------------------------- -
period 1
or
(
period
“PWM Channel Mode Register” on page 916
)
(
------------------------------------------ -
or
CRPD
“PWM Channel Duty Cycle Register” on page 918
(
----------------------------------------------------- -
–
2
⁄
MCK
×
2
×
⁄
CPRD
) 1
DIVB
fchannel_x_clock
–
MCK
period
⁄
(
×
)
period
fchannel_x_clock
DIVB
)
⁄
2
)
×
CDTY
×
CDTY
)
SAM3S Preliminary
(PWM_CPRDx) and the duty-cycle
) )
(PWM_CMRx). This field is
(PWM_CDTYx) to
851