ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 990

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

39.6.12
39.6.13
990
990
SAM3S Preliminary
SAM3S Preliminary
Fault Output
Write Protection Registers
The ADC Controller internal fault output is directly connected to PWM fault input. Fault output
may be asserted according to the configuration of ADC_EMR (Extended Mode Register) and
ADC_CWR (Compare Window Register) and converted values. This fault line can be enabled or
disabled within PWM.
In case it is activated and asserted by ADC Controller the PWM outputs will be immediately
placed in a safe state (pure combinational path).
To prevent any single software error that may corrupt ADC behavior, certain address spaces
can be write-protected by setting the WPEN bit in the
(ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Pro-
tect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the ADC Write Protect Mode Register (ADC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“ADC Mode Register” on page 993
“ADC Channel Sequence 1 Register” on page 996
“ADC Channel Sequence 2 Register” on page 997
“ADC Channel Enable Register” on page 998
“ADC Channel Disable Register” on page 999
“ADC Extended Mode Register” on page 1007
“ADC Compare Window Register” on page 1008
“ADC Channel Gain Register” on page 1009
“ADC Channel Offset Register” on page 1010
“ADC Analog Control Register” on page 1012
“ADC Write Protect Mode Register”
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11