ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 65

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6.2.10
6500C–ATARM–8-Feb-11
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software
request. All interrupts are asynchronous to instruction execution. In the system, peripherals use
interrupts to communicate with the processor.
Table 10-9.
1.
2.
3.
4.
5.
6.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that
figurable priority, see:
Exception
number
1
2
3
4
5
6
7-10
11
12-13
14
15
16 and
above
•
“System Handler Control and State Register” on page 179
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative
See
See
See the “Peripheral Identifiers” section of the datasheet.
See
Increasing in steps of 4.
(1)
values for exceptions other than interrupts. The IPSR returns the Exception number, see
“Interrupt Program Status Register” on page
“Vector table” on page 67
“System Handler Priority Registers” on page
“Interrupt Priority Registers” on page
IRQ
number
1)
-
-14
-13
-12
-11
-10
-
-5
-
-2
-1
0 and
above
Properties of the different exception types
(4)
(
Exception
type
Reset
NMI
Hard fault
Memory
management
fault
Bus fault
Usage fault
-
SVCall
-
PendSV
SysTick
Interrupt (IRQ)
for more information.
Priority
-3, the
highest
-2
-1
Configurable
Configurable
(3)
Configurable
(3)
-
Configurable
(3)
-
Configurable
(3)
Configurable
(3)
Configurable
(3)
(5)
158.
Table 10-9 on page 65
47.
176.
Vector address
or offset
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
Reserved
0x0000002C
Reserved
0x00000038
0x0000003C
0x00000040 and
above
SAM3S Preliminary
(6)
(2)
shows as having con-
Activation
Asynchronous
Asynchronous
-
Synchronous
Synchronous when
precise,
asynchronous when
imprecise
Synchronous
-
Synchronous
-
Asynchronous
Asynchronous
Asynchronous
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