ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 228
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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Figure 12-5. Software Reset
12.3.4.5
228
SRCMP in RSTC_SR
SAM3S Preliminary
Write RSTC_CR
Watchdog Reset
if PROCRST=1
periph_nreset
if PERRST=1
if EXTRST=1
proc_nreset
(nrst_out)
RSTTYP
NRST
SLCK
MCK
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
• If WDRPROC = 1, only the processor reset is asserted.
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
Freq.
Any
Any
Resynch.
1 cycle
Processor Startup
= 2 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x3 = Software Reset
6500C–ATARM–8-Feb-11
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