ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 162
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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10.20.9
10.20.9.1
162
SAM3S Preliminary
Level-sensitive interrupts
Hardware and software control of interrupts
The processor supports level-sensitive interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typ-
ically this happens because the ISR accesses the peripheral, causing it to clear the interrupt
request.
When the processor enters the ISR, it automatically removes the pending state from the inter-
rupt, see
signal is not deasserted before the processor returns from the ISR, the interrupt becomes pend-
ing again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the fol-
lowing reasons:
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pend-
ing to active. Then:
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
• the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
• the NVIC detects a rising edge on the interrupt signal
• software writes to the corresponding interrupt set-pending register bit, see
• Software writes to the corresponding interrupt clear-pending register bit.
pending Registers” on page
Trigger Interrupt Register” on page
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
– If the interrupt signal is not pulsed while the processor is in the ISR, when the
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
processor returns from the ISR the state of the interrupt changes to inactive.
“Hardware and software control of interrupts”
155, or to the STIR to make an SGI pending, see
161.
. For a level-sensitive interrupt, if the
6500C–ATARM–8-Feb-11
“Interrupt Set-
“Software
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