ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 152

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

152
SAM3S Preliminary
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters. For more information see the description of the NVIC_SetPriority function in
programming hints” on page
onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt.
Table 10-28. Mapping of interrupts to the interrupt variables
1.
Interrupts
0-34
35-63
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds
the interrupt priority for interrupt n.
Each array element corresponds to a single NVIC register, for example the element
ICER[0] corresponds to the ICER0 register.
CMSIS array elements
Set-enable
ISER[0]
ISER[1]
Clear-enable
ICER[0]
ICER[1]
163.
Table 10-28
(1)
Set-pending
ISPR[0]
ISPR[1]
shows how the interrupts, or IRQ numbers, map
Clear-pending
ICPR[0]
ICPR[1]
Active Bit
IABR[0]
IABR[1]
6500C–ATARM–8-Feb-11
“NVIC