ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 888

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36.7.9
Name:
Address:
Access:
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
page
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
0 = Manual write of double buffer registers and manual update of synchronous channels. The update occurs at the begin-
ning of the next PWM period, when the bit UPDULOCK in
set.
1 = Manual write of double buffer registers and automatic update of synchronous channels. The update occurs when the
Update Period is elapsed.
2 = Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels. The update
occurs when the Update Period is elapsed.
3 = Reserved.
• PTRM: PDC Transfer Request Mode
• PTRCS: PDC Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
888
UPDM
911.
31
23
15
–
–
7
–
0
1
2
SAM3S Preliminary
PWM Sync Channels Mode Register
PTRCS
PTRM
30
22
14
PWM_SCM
0x40020020
–
–
6
–
Read-write
0
1
x
x
The WRDY flag in
are never set to 1.
The WRDY flag in
update period is elapsed, the PDC transfer request is never set to 1.
The WRDY flag in
are set to 1 as soon as the update period is elapsed.
The WRDY flag in
are set to 1 as soon as the selected comparison matches.
WRDY Flag and PDC Transfer Request
29
21
13
–
–
5
–
PTRM
“PWM Interrupt Status Register 2” on page 895
“PWM Interrupt Status Register 2” on page 895
“PWM Interrupt Status Register 2” on page 895
“PWM Interrupt Status Register 2” on page 895
28
20
12
–
–
4
–
“PWM Sync Channels Update Control Register” on page 889
SYNC3
27
19
11
–
–
–
3
SYNC2
“PWM Write Protect Status Register” on
26
18
10
–
–
–
2
and the PDC transfer request
is set to 1 as soon as the
and the PDC transfer request
and the PDC transfer request
SYNC1
25
17
–
9
–
1
6500C–ATARM–8-Feb-11
UPDM
SYNC0
24
16
–
8
–
0
is