ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 679

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

33.6
33.6.1
33.6.2
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Product Dependencies
I/O Lines
Power Management
The pins used for interfacing the USART may be multiplexed with the PIO lines. The program-
mer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up
on TXD must also be enabled.
All the pins of the modems may or may not be implemented on the USART. Only
equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the
associated control bits and statuses have no effect on the behavior of the USART.
Table 33-3.
The USART is not continuously clocked. The programmer must first enable the USART Clock in
the Power Management Controller (PMC) before using the USART. However, if the application
does not require USART operations, the USART clock can be stopped when not needed and be
restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
Instance
USART0
USART0
USART0
USART0
USART0
USART1
USART1
USART1
USART1
USART1
USART1
USART1
USART1
USART1
I/O Lines
Signal
RXD0
DCD1
DSR1
RXD1
CTS0
RTS0
SCK0
TXD0
CTS1
DTR1
RTS1
SCK1
TXD1
RI1
SAM3S Preliminary
SAM3S Preliminary
I/O Line
PA25
PA26
PA28
PA27
PA29
PA24
PA21
PA23
PA22
PA8
PA7
PA5
PA2
PA6
USART1
Peripheral
A
A
A
B
A
A
A
A
A
A
A
A
A
A
fully
679
679