ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 943
ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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37.7
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write
operations to the UDP registers, including the UDP_TXVC register.
Table 37-6.
Notes:
6500C–ATARM–8-Feb-11
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
...
0x030 + 0x4 * (7 - 1)
0x050
...
0x050 + 0x4 * (7 - 1)
0x070
0x074
0x078 - 0xFC
USB Device Port (UDP) User Interface
1. Reset values are not defined for UDP_ISR.
2. See Warning above the
Register Mapping
Register
Frame Number Register
Global State Register
Function Address Register
Reserved
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Interrupt Clear Register
Reserved
Reset Endpoint Register
Reserved
Endpoint Control and Status Register 0
...
Endpoint Control and Status Register 7
Endpoint FIFO Data Register 0
...
Endpoint FIFO Data Register 7
Reserved
Transceiver Control Register
Reserved
”Register Mapping”
on this page.
Name
UDP_FRM_NUM
UDP_GLB_STAT
UDP_FADDR
–
UDP_IER
UDP_IDR
UDP_IMR
UDP_ISR
UDP_ICR
–
UDP_RST_EP
–
UDP_CSR0
...
UDP_CSR7
UDP_FDR0
...
UDP_FDR7
–
UDP_TXVC
–
(2)
SAM3S Preliminary
Access
Read-only
Read-write
Read-write
–
Write-only
Write-only
Read-only
Read-only
Write-only
–
Read-write
–
Read-write
...
Read-write
Read-write
...
Read-write
–
Read-write
–
0x0000_0000
0x0000_0010
0x0000_0100
0x0000_1200
Reset
–
–
–
0x0000_0000
–
0x0000_0000
...
0x0000_0000
0x0000_0000
...
0x0000_0000
–
0x0000_0100
–
(1)
943
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