ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 987

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Oth-
erwise the parameters of CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as
shown in
Table 39-6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Chan-
nel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode.
Table 39-7.
OFFSET Bit
GAIN<0:1>
Table
00
01
10
11
0
1
Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G)
39-6.
OFFSET (DIFF = 0)
GAIN (DIFF = 0)
(G-1)Vrefin/2
1
1
2
4
0
SAM3S Preliminary
SAM3S Preliminary
OFFSET (DIFF = 1)
GAIN (DIFF = 1)
0.5
1
2
2
0
987
987