ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 854

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36.6.2.3
Figure 36-6. 2-bit Gray Up/Down Counter
36.6.2.4
854
PWML0
PWML1
PWMH0
PWMH1
DOWNx
SAM3S Preliminary
2-bit Gray Up/Down Counter for Stepper Motor
Dead-Time Generator
It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 out-
puts. Dead-Time Generator and other downstream logic can be configured on these channels.
Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration
registers.
When GCEN0 is set to 1, channels 0 and 1 outputs are driven with gray counter.
The dead-time generator uses the comparator output OCx to provide the two complementary
outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control
switches safely. When the dead-time generator is enabled by setting the bit DTE to 1 or 0 in the
“PWM Channel Mode Register”
overlapping times) are inserted between the edges of the two complementary outputs DTOHx
and DTOLx. Note that enabling or disabling the dead-time generator is allowed only if the chan-
nel is disabled.
The dead-time is adjustable by the
puts of the dead-time generator can be adjusted separately by DTH and DTL. The dead-time
values can be updated synchronously to the PWM period by using the
Time Update Register”
The dead-time is based on a specific counter which uses the same selected clock that feeds the
channel counter of the comparator. Depending on the edge and the configuration of the dead-
time, DTOHx and DTOLx are delayed until the counter has reached the value defined by DTH or
DTL. An inverted configuration bit (DTHI and DTLI bit in the PWM_CMRx register) is provided
for each output to invert the dead-time outputs. The following figure shows the waveform of the
dead-time generator.
(PWM_DTUPDx).
GCEN0 = 1
(PWM_CMRx), dead-times (also called dead-bands or non-
“PWM Channel Dead Time Register”
(PWM_DTx). Both out-
“PWM Channel Dead
6500C–ATARM–8-Feb-11