ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 391
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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- Download datasheet (24Mb)
23.13 Slow Clock Mode
23.13.1
Figure 23-28. Read/Write Cycles in Slow Clock Mode
6500C–ATARM–8-Feb-11
A[23:0]
NWE
MCK
NCS
Slow Clock Mode Waveforms
1
SLOW CLOCK MODE WRITE
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because MCK has
been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro-
grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
Figure 23-28
chip selects.
Table 23-4.
Read Parameters
NRD_SETUP
NRD_PULSE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_CYCLE
NWE_CYCLE = 3
1
Table 23-4
illustrates the read and write operations in slow clock mode. They are valid on all
Read and Write Timing Parameters in Slow Clock Mode
1
indicates the value of read and write parameters in slow clock mode.
Duration (cycles)
1
1
0
2
2
Write Parameters
NWE_SETUP
NWE_PULSE
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
A[23:0]
MCK
NRD
NCS
SAM3S Preliminary
SLOW CLOCK MODE READ
1
NRD_CYCLE = 2
1
Duration (cycles)
1
1
0
3
3
391
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