ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 234

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4.3
Name:
Address:
Access:
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2
allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
234
31
23
15
–
–
7
–
SAM3S Preliminary
Reset Controller Mode Register
30
22
14
RSTC_MR
0x400E1408
Read-write
–
–
6
–
29
21
13
–
–
5
URSTIEN
28
20
12
–
–
4
KEY
27
19
11
–
3
–
26
18
10
–
2
–
ERSTL
(ERSTL+1)
25
17
–
9
1
–
Slow Clock cycles. This
6500C–ATARM–8-Feb-11
URSTEN
24
16
–
8
0