ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 411
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 411 of 1118
- Download datasheet (24Mb)
24.4.4
24.4.5
24.4.5.1
24.4.5.2
24.4.5.3
6500C–ATARM–8-Feb-11
Data Transfers
PDC Flags and Peripheral Status Register
Receive Transfer End
Transmit Transfer End
Receive Buffer Full
The following list gives an overview of how status register flags behave depending on the coun-
ters’ values:
These status flags are described in the Peripheral Status Register.
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable
(TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the periph-
eral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC
receive channel which then requests access to the Matrix. When access is granted, the PDC
receive channel starts reading the peripheral Receive Holding Register (RHR). The read data
are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit chan-
nel which then requests access to the Matrix. When access is granted, the PDC transmit
channel reads data from memory and puts them to Transmit Holding Register (THR) of its asso-
ciated peripheral. The same peripheral sends data according to its mechanism.
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the
PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status
Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single
channel or two different channels.
This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred
to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
This flag is set when PERIPH_TCR register reaches zero and the last data has been written into
peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero
and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
• ENDRX flag is set when the PERIPH_RCR register reaches zero.
• RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
• ENDTX flag is set when the PERIPH_TCR register reaches zero.
• TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
SAM3S Preliminary
411
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