ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 713
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 713 of 1118
- Download datasheet (24Mb)
33.7.8.4
33.7.8.5
33.7.8.6
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Receiver and Transmitter Control
Character Transmission
Character Reception
See “Receiver and Transmitter Control” on page 685.
The characters are sent by writing in the Transmit Holding Register (US_THR). An additional
condition for transmitting a character can be added when the USART is configured in SPI mas-
ter mode. In the USART_MR register, the value configured on INACK field can prevent any
character transmission (even if US_THR has been written) while the receiver side is not ready
(character not read). When INACK equals 0, the character is transmitted whatever the receiver
status. If INACK is set to 1, the transmitter waits for the receiver holding register to be read
before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character
loss) on the receiver side.
The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY
(Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates
that all the characters written in US_THR have been processed. When the current character pro-
cessing is completed, the last character written in US_THR is transferred into the Shift Register
of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in
US_THR while TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding
Register (US_THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line
stays at high level during all this time. The UNRE bit is cleared by writing the Control Register
(US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before
the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the
LSB bit. So, the slave select line (NSS) is always released between each character transmission
and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices
supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The
slave select line (NSS) can be released at high level only by writing the Control Register
(US_CR) with the RTSDIS bit to 1 (for example, when all data have been transferred to the slave
device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS)
to initiate a character transmission but only a low level. However, this low level must be present
on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to
the MSB bit.
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred
into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control
Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the
frame must ensure a minimum delay of 1 Tbit between each character transmission. The
receiver does not require a falling edge of the slave select line (NSS) to initiate a character
SAM3S Preliminary
SAM3S Preliminary
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