ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 374

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.8.4
23.8.4.1
23.8.4.2
374
SAM3S Preliminary
Write Mode
Write is Controlled by NWE (WRITE_MODE = 1):
Write is Controlled by NCS (WRITE_MODE = 0)
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi-
cates which signal controls the write operation.
Figure 23-11
put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are
turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the
programmed waveform on NCS.
Figure 23-11. WRITE_MODE = 1. The write operation is controlled by NWE
Figure 23-12
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
Figure 23-12. WRITE_MODE = 0. The write operation is controlled by NCS
A [23:0]
A [23:0]
D[7:0]
D[7:0]
NWE
NWE
MCK
MCK
NCS
NCS
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
6500C–ATARM–8-Feb-11