ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 697

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 33-23. Timeguard Operations
33.7.3.11
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
Receiver Time-out
Start
Bit
D0
D1
Table 33-10
in relation to the function of the Baud Rate.
Table 33-10. Maximum Timeguard Length Depending on Baud Rate
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed to
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains to 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
D2
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (US_CR) with the STTTO (Start Time-out) bit to 1. In this case, the idle state
D3
D4
D5
Baud Rate
115200
indicates the maximum length of a timeguard period that the transmitter can handle
Bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
D6
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
Bit time
69.4
52.1
34.7
29.9
17.9
17.4
833
104
8.7
µs
D1
D2
D3
D4
SAM3S Preliminary
SAM3S Preliminary
D5
D6
D7
Parity
Bit
Stop
Bit
Timeguard
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
ms
TG = 4
697
697