ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 436

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.13 Programming Sequence
436
SAM3S Preliminary
1. Enabling the Main Oscillator:
2. Checking the Main Oscillator Frequency (Optional):
3. Setting PLL and Divider:
4. Selection of Master Clock and Processor Clock
In some situations the user may need an accurate measure of the main clock frequency.
This measure can be accomplished via the CKGR_MCFR register.
Once the MAINFRDY field is set in CKGR_MCFR register, the user may read the MAINF
field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen
slow clock cycles.
All parameters needed to configure PLL and the divider are located in the CKGR_PLLxR
register.
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the
PMC_SR register after CKGR_PLLR register has been written.
Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set
in the PMC_SR register. This can be done either by polling the status register or by waiting
the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the
PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single write
operation. If at some stage one of the following parameters, MUL, DIV is modified, LOCK bit
will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again.
The user is constrained to wait for LOCK bit to be set before using the PLL output clock.
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by polling the status register or by
The main oscillator is enabled by setting the MOSCXTEN field in the CKGR_MOR reg-
ister. The user can define a start-up time. This can be achieved by writing a value in the
MOSCXTST field in the CKGR_MOR register. Once this register has been correctly
configured, the user must wait for MOSCXTS field in the PMC_SR register to be set.
This can be done either by polling the status register, or by waiting the interrupt line to
be raised if the associated interrupt to MOSCXTS has been enabled in the PMC_IER
register.
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
6500C–ATARM–8-Feb-11