ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 368

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.8
23.8.1
23.8.1.1
23.8.1.2
368
Standard Read and Write Protocols
SAM3S Preliminary
Read Waveforms
NRD Waveform
NCS Waveform
In the following sections, NCS represents one of the NCS[0..3] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus.
Figure 23-5. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the
falling edge;
rising edge;
rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
A[23:0]
D[7:0]
MCK
NRD
NCS
NCS_RD_SETUP
NRD_SETUP
Figure
23-5.
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NRD_HOLD
NCS_RD_HOLD
6500C–ATARM–8-Feb-11