ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 51

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ATSAM3S-EK

Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Datasheets

Specifications of ATSAM3S-EK

Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
10.4.3.15
• Active stack pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
• Thread mode privilege level
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CON-
TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and
exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruc-
tion to set the Active stack pointer bit to 1, see
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This
ensures that instructions after the ISB execute using the new stack pointer. See
6500C–ATARM–8-Feb-11
31
23
15
7
CONTROL register
30
22
14
6
The CONTROL register controls the stack used and the privilege level for software execution
when the processor is in Thread mode. See the register summary in
its attributes. The bit assignments are:
29
21
13
5
Reserved
“MSR” on page
28
20
12
4
Reserved
Reserved
Reserved
144.
27
19
11
3
“ISB” on page 142
26
18
10
2
SAM3S Preliminary
Active Stack
Table 10-2 on page 44
Pointer
25
17
9
1
Thread Mode
Privilege
Level
24
16
8
0
for
51

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