ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 220

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.6
11.5.6.1
220
SAM3S Preliminary
ITM (Instrumentation Trace Macrocell)
How to Configure the ITM
The DWT contains counters for the items that follow:
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
The following example describes how to output trace data in asynchronous trace mode.
• Watchpoint event to halt core
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
• Software trace: Software can write directly to ITM stimulus registers. This can be done
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
• Configure the TPIU for asynchronous trace mode (refer to
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
• Write 0x00010015 into the Trace Control Register:
• Write 0x1 into the Trace Enable Register:
• Write 0x1 into the Trace Privilege Register:
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
thanks to the “printf” function. For more information, refer to
Configure the
counter to generate the timestamp.
Configure the
Lock Access Register (Address: 0xE0000FB0)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
– Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
– Fix the ATB ID to 1
– Enable the Stimulus port 0
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
ITM”.
TPIU”)
Section 11.5.6.3 “5.4.3. How to
Section 11.5.6.1 “How to
6500C–ATARM–8-Feb-11