ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 675

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

33. Universal Synchronous Asynchronous Receiver Transmitter (USART)
33.1
33.2
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely programma-
ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements parity error, framing error and overrun error detection. The receiver time-out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 and SPI buses,
with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem
ports. The hardware handshaking feature enables an out-of-band flow control by automatic
management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data
transfers to the transmitter and from the receiver. The PDC provides chained buffer manage-
ment without any intervention of the processor.
• Programmable Baud Rate Generator
• 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
• RS485 with Driver Control Signal
• ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
• IrDA Modulation and Demodulation
• SPI Mode
• Test Modes
• Supports Connection of Two Peripheral DMA Controller Channels (PDC)
– 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
– Parity Generation and Error Detection
– Framing Error Detection, Overrun Error Detection
– MSB- or LSB-first
– Optional Break Generation and Detection
– By 8 or by 16 Over-sampling Receiver Frequency
– Optional Hardware Handshaking RTS-CTS
– Optional Modem Signal Management DTR-DSR-DCD-RI
– Receiver Time-out and Transmitter Timeguard
– Optional Multidrop Mode with Address Generation and Detection
– NACK Handling, Error Counter with Repetition and Iteration Limit
– Communication at up to 115.2 Kbps
– Master or Slave
– Serial Clock Programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
– Remote Loopback, Local Loopback, Automatic Echo
– Offers Buffer Transfer without Processor Intervention
SAM3S Preliminary
SAM3S Preliminary
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