ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 781

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

34.7.11
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = counter is incremented on rising edge of the clock.
1 = counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare
0 = counter clock is not stopped when counter reaches RC.
1 = counter clock is stopped when counter reaches RC.
6500C–ATARM–8-Feb-11
CPCDIS
Value
Value
WAVE
0
1
2
3
4
5
6
7
0
1
2
3
31
23
15
7
TC Channel Mode Register: Waveform Mode
BSWTRG
ASWTRG
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Name
NONE
XC0
XC1
XC2
CPCSTOP
30
22
14
TC_CMRx [x=0..2] (WAVE = 1)
0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Read-write
6
WAVSEL
Description
Clock selected: TCLK1
Clock selected: TCLK2
Clock selected: TCLK3
Clock selected: TCLK4
Clock selected: TCLK5
Clock selected: XC0
Clock selected: XC1
Clock selected: XC2
Description
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
29
21
13
5
BURST
BEEVT
AEEVT
ENETRG
28
20
12
4
“TC Write Protect Mode Register” on page 778
CLKI
27
19
11
3
BCPC
ACPC
EEVT
26
18
10
2
SAM3S Preliminary
TCCLKS
25
17
9
1
EEVTEDG
BCPB
ACPA
24
16
8
0
781