ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 219

• Manufacturer Part Number: ATSAM3S-EK
• Description: KIT EVAL FOR ATSAM3S4C
• Manufacturer: Atmel
• Series: SAM3Sr
• Type: MCUr

Specifications of ATSAM3S-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex-M3
• Kit Contents: Board
• Features: TFT Colour LCD Display, SD/MMC Interface
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.3.1
11.5.4
11.5.5
6500C–ATARM–8-Feb-11
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
SW-DP and JTAG-DP Selection Mechanism
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asyn-
chronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace
can only be used with SW-DP, not JTAG-DP.
Table 11-2.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly
between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after
JTAGSEL is changed.
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-
DP is selected by default after reset.
The FPB:
The FPB unit contains:
The DWT contains four comparators which can be configured to generate the following:
Pin Name
TMS/SWDIO
TCK/SWCLK
TDI
TDO/TRACESWO
• Switch from JTAG-DP to SW-DP. The sequence is:
• Switch from SWD to JTAG. The sequence is:
• Implements hardware breakpoints
• Patches code and data from code space to system space.
• Two literal comparators for matching against literal loads from Code space, and remapping to
• Six instruction comparators for matching against instruction fetches from Code space and
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the
• PC sampling packets at set intervals
• PC or Data watchpoint packets
a corresponding area in System space.
remapping to a corresponding area in System space.
processor core on a match.
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
SWJ-DP Pin List
JTAG Port
TMS
TDO
TCK
TDI
SAM3S Preliminary
TRACESWO (optional: trace)
Serial Wire Debug Port
SWCLK
SWDIO
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