LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 136

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
Table 120. Pin description
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
UM10237_4
User manual
Symbol
V
V
V
V
n.c.
V
V
VREF
VBAT
SSIO
SSCORE
SSA
DD(3V3)
DD(DCDC)(3V3)
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
Pad provides special analog functionality.
Ball
H4, P4,
L9, L13,
G13,
D13,
C11,
B4
H3, L8,
A10
F3
E2, L4,
K8, L11,
J14, E12,
E10,
C5
H1, L12,
G10
G1, N9,
E9
F2
G2
K1
[10]
[14]
[9]
[13]
[14]
[11]
[14]
[9]
[12]
…continued
Type
I
I
I
I
I
I
I
I
I
Description
ground: 0 V reference for the digital IO pins.
ground: 0 V reference for the core.
analog ground: 0 V reference. This should nominally be the same voltage as
V
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
not connected pins: These pins must be left unconnected (floating).
3.3 V DC-to-DC converter supply voltage: This is the power supply for the
on-chip DC-to-DC converter.
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
to power the ADC and DAC.
ADC reference: This should be nominally the same voltage as V
should be isolated to minimize noise and error. The level on this pin is used as a
reference for ADC and DAC.
RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
SSIO
DD(3V3)
/V
Rev. 04 — 26 August 2009
SSCORE
but should be isolated to minimize noise and error. This voltage is used
2
C-bus 400 kHz specification. It requires an external pull-up to provide output
, but should be isolated to minimize noise and error.
2
C-bus is floating and does not disturb the I
Chapter 8: LPC24XX Pin configuration
UM10237
2
© NXP B.V. 2009. All rights reserved.
C lines. Open-drain
DD(3V3)
but
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