LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 575

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I
the data direction bit (R/W) should be 1 to indicate a read.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table
After a repeated START condition, I
Fig 112. Format in the Master Transmitter mode
Fig 113. Format of Master Receive mode
S
from Master to Slave
from Slave to Master
S
from Master to Slave
from Slave to Master
22–526.
SLAVE ADDRESS
SLAVE ADDRESS
Rev. 04 — 26 August 2009
2
C Data Register (I2DAT), and then clear the SI bit. In this case,
“0” - write
“1” - read
“0” - write
“1” - read
RW
R
2
C may switch to the master transmitter mode.
A
A
Chapter 22: LPC24XX I
DATA
DATA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
(n Bytes + Acknowledge)
(n Bytes + Acknowledge)
data transferred
data transferred
A
A
DATA
DATA
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
A/A
A
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2
C0/1/2
P
P