LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 95

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
10.25 Static Memory Page Mode Read Delay registers
10.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 -
Table 92.
(EMCStaticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270)
The EMCStaticWaitPage0-3 registers enable you to program the delay for asynchronous
page mode sequential accesses. It is recommended that these registers are modified
during system initialization, or when there are no current or outstanding transactions. This
can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode. This register is accessed with one wait state.
Table 5–93
Table 93.
0xFFE0 8214, 234, 254, 274)
The EMCStaticWaitWr0-3 registers enable you to program the delay from the chip select
to the write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode.These registers are not used if the extended wait (EW) bit is enabled in the
EMCStaticConfig register. These registers are accessed with one wait state.
Table 5–94
Bit
4:0
31:5
Bit
4:0
31:5
Symbol
Non-page mode
read wait states
or asynchronous
page mode
readfirst access
wait state
(WAITRD)
-
Symbol
Asynchronous
page mode read
after the first
read wait states
(WAITPAGE)
-
Static Memory Read Delay registers (EMCStaticWaitRd0-3 - address 0xFFE0 820C,
0xFFE0 822C, 0xFFE0 824C, 0xFFE0 826C) bit description
Static Memory Page Mode Read Delay registers0-3 (EMCStaticWaitPage0-3 -
address 0xFFE0 8210, 0xFFE0 8230, 0xFFE0 8250, 0xFFE0 8270) bit description
shows the bit assignments for the EMCStaticWaitPage0-3 registers.
shows the bit assignments for the EMCStaticWaitWr0-3 registers.
Rev. 04 — 26 August 2009
0x0 -
0x1E
0x1F
Value Description
-
Value Description
0x0 -
0x1E
0x1F
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Number of wait states for asynchronous page mode read
accesses after the first read:
(n+ 1) CCLK cycle read access time. For asynchronous
page mode read for sequential reads, the wait state time
for page mode accesses after the first read is
(WAITPAGE + 1) x tCCLK.
32 CCLK cycle read access time (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Non-page mode read or asynchronous page mode read,
first read only:
(n + 1) CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD +
1) x tCCLK.
32 CCLK cycles for read accesses (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
95 of 792
Reset
Value
0x1F
NA
Reset
Value
0x1F
NA