LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 274

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
Fig 35. Transmit Active/Inactive state machine
TxProduceIndex <> TxConsumeIndex
9.17 Transmission padding and CRC
TxEnable = 1
After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set
in the Command register and the Produce and Consume indices are not equal, the state
machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the
transmit datapath has completed all pending transmissions, including committing the
transmission status to memory, the state machine returns to the INACTIVE state. The
state machine will also return to the INACTIVE state if the Produce and Consume indices
are equal again i.e. all frames have been transmitted.
For the state machine in
after a soft reset the transmit datapath is inactive until the datapath is re-enabled.
In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet
block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check
Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’
(ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the
MAC2 configuration register, as well as the Override and Pad bits from the transmit
descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and
‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and
CRC bits from the transmit descriptor Control word.
The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable
(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the
descriptor.
If padding is required and enabled, a CRC will always be appended to the padded frames.
A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is
set.
AND
Rev. 04 — 26 August 2009
Figure
TxStatus = 1
TxStatus = 0
INACTIVE
ACTIVE
11–35, a soft reset is like a hardware reset assertion, i.e.
TxEnable = 0 and not busy transmitting
TxProduceIndex = TxConsumeIndex
reset
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Chapter 11: LPC24XX Ethernet
OR
UM10237
© NXP B.V. 2009. All rights reserved.
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