LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 526

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

1. Basic configuration
2. Features
3. SPI overview
4. SPI data transfers
UM10237_4
User manual
The SPI is configured using the following registers:
SPI is a full duplex serial interfaces. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
Figure 19–94
that are available with the SPI. This timing diagram illustrates a single 8 bit data transfer.
The first thing you should notice in this timing diagram is that it is divided into three
horizontal parts. The first part describes the SCK and SSEL signals. The second part
describes the MOSI and MISO signals when the CPHA variable is 0. The third part
describes the MOSI and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with
CPOL set to both 0 and 1. The second point to note is the activation and de-activation of
the SSEL signal. When CPHA = 0, the SSEL signal will always go inactive between data
transfers. This is not guaranteed when CPHA = 1 (the signal can remain active).
1. Power: In the PCONP register
2. Clock: In PCLK_SEL0 select PCLK_SPI (see
3. Pins: Select SPI pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
4. Interrupts: Interrupts are enabled in the S0SPINT register
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•
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UM10237
Chapter 19: LPC24XX SPI
Rev. 04 — 26 August 2009
Remark: On reset, the SPI is enabled (PCSPI = 1).
must be scaled down (see
PINMODE4 (see
are enabled in the VIC using the VICIntEnable register
Remark: In the VIC, the SPI shares its interrupts with the SSP0 interface.
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex Communication.
SPI master or slave.
Maximum data bit rate of one eighth of the input clock rate.
8 to 16 bits per transfer.
is a timing diagram that illustrates the four different data transfer formats
Section
Rev. 04 — 26 August 2009
9–5).
Section
(Table
19–7.4).
4–63), set bit PCSPI.
Table
4–56). In master mode, the clock
(Table
Section
7–106).
19–7.7. Interrupts
© NXP B.V. 2009. All rights reserved.
User manual
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