LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 428

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
4.4 UARTn Interrupt Enable Register (U0IER - 0xE000 C004, U2IER -
higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by
zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order
to access the UARTn Divisor Latches.
Table 380. UARTn Divisor Latch LSB Register (U0DLL - address 0xE000 C000,
Table 381. UARTn Divisor Latch MSB Register (U0DLM - address 0xE000 C004,
0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0)
The UnIER is used to enable the three UARTn interrupt sources.
Table 382. UARTn Interrupt Enable Register (U0IER - address 0xE000 C004,
Bit
7:0
Bit
7:0
Bit
0
1
2
7:3
8
9
31:10 -
Symbol
DLLSB
Symbol
DLMSB
Symbol
RBR
Interrupt
Enable
THRE
Interrupt
Enable
RX Line
Status
Interrupt
Enable
-
ABEOIntEn
ABTOIntEn
U2DLL - 0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) bit description
U2DLM - 0xE007 8004, U3DLM - 0xE007 C004 when DLAB = 1) bit description
U2IER - 0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0) bit description
Description
The UARTn Divisor Latch LSB Register, along with the UnDLM
register, determines the baud rate of the UARTn.
Description
The UARTn Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UARTn.
Value Description
0
1
0
1
0
1
0
1
0
1
Rev. 04 — 26 August 2009
enables the Receive Data Available interrupt for UARTn. It
also controls the Character Receive Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
enables the THRE interrupt for UARTn. The status of this
can be read from UnLSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
enables the UARTn RX line status interrupts. The status of
this interrupt can be read from UnLSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
enables the end of auto-baud interrupt.
Disable End of Auto-baud Interrupt.
Enable End of Auto-baud Interrupt.
enables the auto-baud time-out interrupt.
Disable Auto-baud Time-out Interrupt.
Enable Auto-baud Time-out Interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0x01
Reset Value
0x00
Reset
Value
0
0
0
NA
0
0
NA
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