LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 485

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
8.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR -
Table 424. Interrupt Enable Register (CAN1IER - address 0xE004 4010, CAN2IER - address
0xE004 8014)
This register controls how various CAN timings are derived from the APB clock. It defines
the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW).
Furthermore, it defines the length of the bit period, the location of the sample point and the
number of samples to be taken at each sample point. It can be read at any time but can
only be written if the RM bit in CANmod is 1.
Bit
0
1
2
3
4
5
6
7
8
9
10
31:11
Symbol Function
RIE
TIE1
EIE
DOIE
WUIE
EPIE
ALIE
BEIE
IDIE
TIE2
TIE3
-
0xE004 8010) bit description
Receiver Interrupt Enable. When the Receive Buffer Status is 'full',
the CAN Controller requests the respective interrupt.
Transmit Interrupt Enable for Buffer1. When a message has been
successfully transmitted out of TXB1 or Transmit Buffer 1 is
accessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.
Error Warning Interrupt Enable. If the Error or Bus Status change
(see Status Register), the CAN Controller requests the respective
interrupt.
Data Overrun Interrupt Enable. If the Data Overrun Status bit is
set (see Status Register), the CAN Controller requests the
respective interrupt.
Wake-Up Interrupt Enable. If the sleeping CAN controller wakes
up, the respective interrupt is requested.
Error Passive Interrupt Enable. If the error status of the CAN
Controller changes from error active to error passive or vice versa,
the respective interrupt is requested.
Arbitration Lost Interrupt Enable. If the CAN Controller has lost
arbitration, the respective interrupt is requested.
Bus Error Interrupt Enable. If a bus error has been detected, the
CAN Controller requests the respective interrupt.
ID Ready Interrupt Enable. When a CAN identifier has been
received, the CAN Controller requests the respective interrupt.
Transmit Interrupt Enable for Buffer2. When a message has been
successfully transmitted out of TXB2 or Transmit Buffer 2 is
accessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.
Transmit Interrupt Enable for Buffer3. When a message has been
successfully transmitted out of TXB3 or Transmit Buffer 3 is
accessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
NA
485 of 792
RM
Set
X
X
X
X
X
X
X
X
X
X
X