LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 683

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
9. ISP commands
UM10237_4
User manual
Table 602. Code Read Protection hardware/software interaction
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupoorted or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
The following commands are accepted by the ISP command handler. Detailed status
codes are supported for each command. The command handler sends the return code
INVALID_COMMAND when an undefined command is received. Commands and return
codes are in ASCII format.
CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"
commands.
Table 603. ISP command summary
CRP option
No
No
No
CRP1
CRP1
CRP2
CRP2
CRP3
CRP1
CRP2
CRP3
ISP Command
Unlock
Set Baud Rate
Echo
Write to RAM
Read Memory
Prepare sector(s) for
write operation
Copy RAM to Flash
Go
Erase sector(s)
Blank check sector(s)
User Code
Valid
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Rev. 04 — 26 August 2009
E <start sector number> <end sector number>
Usage
U <Unlock Code>
B <Baud Rate> <stop bit>
A <setting>
W <start address> <number of bytes>
R <address> <number of bytes>
P <start sector number> <end sector number>
C <Flash address> <RAM address> <number of bytes>
G <address> <Mode>
I <start sector number> <end sector number>
Chapter 30: LPC24XX Flash memory programming firmware
P2.10 pin at
reset
X
High
Low
High
Low
High
Low
x
x
x
x
JTAG enabled LPC2400
Yes
Yes
Yes
No
No
No
No
No
No
No
No
enters ISP
mode
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
UM10237
© NXP B.V. 2009. All rights reserved.
partial Flash
Update in ISP
mode
Yes
NA
Yes
NA
Yes
NA
No
NA
Yes
No
No
Described in
Table 30–604
Table 30–605
Table 30–607
Table 30–608
Table 30–609
Table 30–610
Table 30–611
Table 30–612
Table 30–613
Table 30–614
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