LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 718

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
5. Programming the GPDMA
UM10237_4
User manual
5.1 Enabling the GPDMA
5.2 Disabling the GPDMA
Table 651. DMA Connections
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream is
configured to provide unidirectional DMA transfers for a single source and destination.
The source and destination areas can each be either a memory region or a peripheral
which supports the GPDMA, and must be accessible through AHB1.
The following applies to the registers used in the GPDMA:
To enable the GPDMA set the DMA Enable bit in the DMACConfiguration Register
(Section 32–6.1.13 “Configuration Register (DMACConfiguration - 0xFFE0
To disable the GPDMA:
Peripheral Function DMA Single
SSP1 Rx
SD/MMC
I
I
2
2
1. Read the DMACEnbldChns Register and ensure that all the DMA channels have
2. Disable the GPDMA by writing 0 to the DMA Enable bit in the DMACConfiguration
•
•
•
•
•
S channel 0
S channel 1
Reserved or unused address locations must not be accessed because this can result
in unpredictable behavior of the device.
Reserved or unused bits of registers must be written as zero, and ignored on read
unless otherwise stated in the relevant text.
All register bits are reset to a logic 0 by a system or power-on reset unless otherwise
stated in the relevant text.
Unless otherwise stated in the relevant text, all registers support read and write
accesses. A write updates the contents of a register and a read returns the contents
of the register.
All registers defined in this document can only be accessed using word reads and
word writes (i.e. 32 bit accesses), unless otherwise stated in the relevant text.
been disabled. If any channels are active, see
channel”.
Register
- 0xFFE0 4110 and DMACC1Configuration - 0xFFE0
(Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Request Input
3
4
-
-
Rev. 04 — 26 August 2009
DMA Burst
Request Input
3
4
5
6
Section 32–5.4 “Disabling a DMA
DMA Last Word
Request Input
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4
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4130)”).
UM10237
© NXP B.V. 2009. All rights reserved.
DMA Last Burst
Request Input
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4
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4030)”.
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