LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 717
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
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UM10237_4
User manual
4.2.10 Channel hardware
4.2.12 Interrupt generation
4.2.13 The completion of the DMA transfer indication
4.2.11 DMA request priority
4.3 DMA system connections
Each stream is supported by a dedicated hardware channel, including source and
destination controllers, and a FIFO. This enables better latency than a DMA controller with
only a single hardware channel shared between several DMA streams and simplifies the
control logic.
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 1
has the lowest priority.
If the GPDMA is transferring data for the lower priority channel and then the higher priority
channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword. Channel 1 in the
GPDMA is designed so that it cannot saturate the AHB bus. If it goes active, the GPDMA
relinquishes control of the bus (for a bus cycle), after four transfers of the programmed
size (irrespective of the size of transfer). This enables other AHB masters to access the
bus.
It is recommended that memory-to-memory transactions use the low priority channel.
Otherwise other (lower priority) AHB bus masters are prevented from accessing the bus
during GPDMA memory-to-memory transfer.
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the GPDMA, and is connected to the LPC2400 interrupt controller.
The completion of the DMA transfer is indicated by:
According to
Last Word Request Input nor DMA Last Burst Request Input. Therefore there will be no
indication of completion if SSP0, SSP1 and I2S are performing the flow control.
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals.
numbers used by the supported peripherals.
Table 651. DMA Connections
Peripheral Function DMA Single
SSP0 Tx
SSP0 Rx
SSP1 Tx
1. The transfer count reaching 0 if the GPDMA is performing flow control, OR
2. The peripheral setting the DMA Last Word Request Input (DMACLSREQ) or the DMA
Last Burst Request Input (DMALBREQ) if the peripheral is performing flow control.
Table 32–651 “DMA
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Request Input
0
1
2
Rev. 04 — 26 August 2009
Connections”, SSP0, SSP1 and I2S do not use DMA
DMA Burst
Request Input
0
1
2
Table 32–651
DMA Last Word
Request Input
-
-
-
shows the DMA Request
UM10237
© NXP B.V. 2009. All rights reserved.
DMA Last Burst
Request Input
-
-
-
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