LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 713

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
Fig 144. GPDMA block diagram
4.2.1 AHB Slave Interface
4.2.2 Control Logic and Register Bank
4.2.3 DMA Request and Response Interface
responses
Interrupts
requests
AHB BUS
DMA
DMA
DMA
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
Figure 32–144
The functions of the GPDMA are described in the following sections:
All transactions on the AHB slave programming bus of the GPDMA are 32 bit wide.
The register block stores data written, or to be read across the AHB interface.
See DMA Interface description for information on the DMA request and response
interface.
•
•
•
•
•
•
•
•
AHB slave interface
Control logic and register bank
DMA request and response interface
Channel logic and channel register bank
Interrupt request
AHB master interface
Channel hardware
DMA request priority
INTERFACE
INTERFACE
INTERRUPT
AHB SLAVE
RESPONSE
REQUEST
REQUEST
DMA
AND
shows a block diagram of the GPDMA.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
REGISTERS
REGISTERS
LOGIC AND
LOGIC AND
CONTROL
CHANNEL
GPDMA
INTERFACE
MASTER
AHB
AHB BUS
UM10237
© NXP B.V. 2009. All rights reserved.
713 of 792