LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 181

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
5.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008)
5.4 Pin Function Select Register 3 (PINSEL3 - 0xE002 C00C)
Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description
[1]
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table
enhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.
Table 132. Pin function select register 2 (PINSEL2 - address 0xE002 C008) bit description
The PINSEL3 register controls the functions of the pins as per the settings listed in
Table
enhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.
LCD functions are available in LPC2470/78 only and are selected in
PINSEL1 Pin
27:26
29:28
31:30
PINSEL2 Pin
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
29:28
31:30
Pins P027] and P0[28] are open-drain for I
9–132. The direction control bit in the IO1DIR register (or the FIO1DIR register if the
9–133. The direction control bit in the IO1DIR register (or the FIO1DIR register if the
name
P0[29]
P0[30]
P0[31]
name
P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]
P1[8]
P1[9]
P1[10]
P1[11]
P1[12]
P1[13]
P1[14]
P1[15]
Function when
00
GPIO Port 0.29 USB_D+1
GPIO Port 0.30 USB_D−1
GPIO Port 0.31 USB_D+2
Function when
00
GPIO Port 1.0
GPIO Port 1.1
GPIO Port 1.2
GPIO Port 1.3
GPIO Port 1.4
GPIO Port 1.5
GPIO Port 1.6
GPIO Port 1.7
GPIO Port 1.8
GPIO Port 1.9
GPIO Port 1.10 ENET_RXD1
GPIO Port 1.11
GPIO Port 1.12 ENET_RXD3
GPIO Port 1.13 ENET_RX_DV
GPIO Port 1.14 ENET_RX_ER
GPIO Port 1.15 ENET_REF_CLK
Rev. 04 — 26 August 2009
Function when
01
ENET_TXD0
ENET_TXD1
ENET_TXD2
ENET_TXD3
ENET_TX_EN
ENET_TX_ER
ENET_TX_CLK
ENET_COL
ENET_CRS_DV/
ENET_CRS
ENET_RXD0
ENET_RXD2
/ENET_RX_CLK
Function
when 01
2
C0 and GPIO functionality for I
Function
when 10
Reserved
Reserved
Reserved
Function
when 10
Reserved
Reserved
MCICLK
MCICMD
Reserved
MCIPWR
MCIDAT0
MCIDAT1
Reserved
Reserved
Reserved
MCIDAT2
MACIDAT3
Reserved
Reserved
Reserved
Chapter 9: LPC24XX Pin connect
2
C-bus compliance.
Function
when 11
Reserved
Reserved
Reserved
Function
when 11
Reserved
Reserved
PWM0[1]
PWM0[2]
Reserved
PWM0[3]
PWM0[4]
PWM0[5]
Reserved
Reserved
Reserved
PWM0[6]
PCAP0[0]
Reserved
Reserved
Reserved
Table
UM10237
© NXP B.V. 2009. All rights reserved.
9–145.
Reset
value
00
00
00
181 of 792
Reset
value
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00