LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 679

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
5.2.10 RAM used by RealMonitor
5.2.4 ISP flow control
5.2.5 ISP command abort
5.2.6 Interrupts during ISP
5.2.7 Interrupts during IAP
5.2.8 RAM used by ISP command handler
5.2.9 RAM used by IAP command handler
A description of UU-encode is available at the wotsit webpage.
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to
stop the flow of data. Data flow is resumed by sending the ASCII control character DC1
(start). The host should also support the same flow control scheme.
Commands can be aborted by sending the ASCII control character "ESC". This feature is
not documented as a command under "ISP Commands" section. Once the escape code is
received the ISP command handler waits for a new command.
The boot block interrupt vectors located in the boot block of the Flash are active after any
reset.
The on-chip Flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user Flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a Flash erase/write IAP
call. The IAP code does not use or disable interrupts.
ISP commands use on-chip RAM from 0x4000 0120 to 0x4000 01FF. The user could use
this area, but the contents may be lost upon reset. Flash programming commands use the
top 32 bytes of on-chip RAM. The stack is located at RAM top - 32. The maximum stack
usage is 256 bytes and it grows downwards.
Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stack
usage in the user allocated stack space is 128 bytes and it grows downwards.
The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. The user could
use this area if RealMonitor based debug is not required. The Flash boot loader does not
initialize the stack for RealMonitor.
Rev. 04 — 26 August 2009
Chapter 30: LPC24XX Flash memory programming firmware
UM10237
© NXP B.V. 2009. All rights reserved.
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