LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 600

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
Table 529. Miscellaneous states
UM10237_4
User manual
Status
Code
(I2CSTAT)
0xF8
0x00
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
9.6 Some special cases
9.7 Simultaneous repeated START conditions from two masters
9.8 Data transfer after loss of arbitration
9.9 Forced access to the I
2
The I
during a serial transfer:
A repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
repeated START condition (see
either master since they were both transmitting the same data.
If the I
a repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure
0x68, 0x78, and 0xB0 (see
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
C block
2
C bus
2
C hardware has facilities to handle the following special cases that may occur
2
22–118). Loss of arbitration is indicated by the following states in I2STAT; 0x38,
C hardware detects a repeated START condition on the I
Application software response
To/From I2DAT
No I2DAT action
No I2DAT action
Rev. 04 — 26 August 2009
Figure 22–120
To I2CON
STA STO SI
0
2
C bus
No I2CON action
Figure
1
22–124). Until this occurs, arbitration is not lost by
0
Chapter 22: LPC24XX I
and
AA
X
Figure
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
22–121).
2
C bus before generating
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
2
C hardware
2
600 of 792
C block
2
C0/1/2
2
C