LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 714

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
Fig 145. GPDMA in the LPC24XX
EXTERNAL
MEMORY
4.2.4 Channel Logic and Channel Register Bank
4.2.5 Interrupt Request
4.2.6 AHB Master Interface
4.2.7 Bus and transfer widths
4.2.8 Endian behavior
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
The interrupt request generates interrupts to the ARM processor.
The GPDMA contains a full AHB master. See
connected in the LPC24XX.
The AHB master is capable of dealing with all types of AHB transactions, including:
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths, and can be the same width or narrower than the physical bus width. The
GPDMA packs or unpacks data as appropriate.
The GPDMA can cope with both little-endian and big-endian addressing. You can set the
endianness of each AHB master individually.
Internally the GPDMA treats all data as a stream of bytes instead of 16 bit or 32 bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32 bit data
bus is observed.
Note: If you do not require byte swapping then avoid using different endianness between
the source and destination addresses.
CONTROLLER
EXTERNAL
•
•
•
MEMORY
Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the GPDMA stalls and waits until the transaction can complete.
Locked transfers for source and destination of each stream.
Setting of protection bits for transfers on each stream.
BRIDGE
ARM7
AHB
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
AHB1
SLAVE
AHB
GPDMA
SRAM
16 kB
MASTER
AHB
Figure 32–145
BRIDGE
APB
for how the GPDMA is
UM10237
SD/MMC
© NXP B.V. 2009. All rights reserved.
SSP1
SSP0
I2S1
I2S0
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